USA: +1 (725) 712-1730
USA: +1 (725) 712-1730

Question & Answer: Your task is to model the following circuit using gate level primitives given the following Verilog module skeleto…..

CECS 225 Digital Logic and Assembly Programing Fall 2017 Your task is to model the following circuit using gate level primitives given the following Verilog module skeleton. Name your gates according to the logic diagram below and use wires properly: 1 module cout (input a,b,c, output cout); 4 wire x, y, Z; cout 8 g3 10 13 endmodule Once you have created the cout module, use the given tester to check for correctness and the test results shown on the right should be produced: testing cout functionality 1// Code your testbench here 2// or browse Examples 3 module coutTester; 4 reg a,b,c 1 wire cout; 1 7 cout dut (a,b,c,cout); 9 integer i; 10 1initial begin 12displayCtesting cout functionality 13isplay(altbltct/tcout 14 SisplayC- 1 1 1 16 17 18 19 20 end 21 endmodule begin a,b,c; #1 $display(%bt%bt%bt|t%b,a,b,c,cout); end WHAT TO TURN IN: Once your cout module is working correctly: Copy the contents of your cout module to a file named cout.txt upload cout.txt to the beachboard dropbox for Lab2 . * Lab 1 Page 3 of3

Your task is to model the following circuit using gate level primitives given the following Verilog module skeleton. Name your gates according to the logic diagram below and use wires properly: Once you have created the cout module, use the given tester to check for correctness and the test results shown on the right should be produced: WHAT TO TURN IN: Once your cout module is working correctly: Copy the contents of your cout module to a file named cout.txt upload cout.txt to the beachboard dropbox for Lab2

Expert Answer

 

module cout(input a,b,c, output cout);

wire x,y,z;

and g1(x,a,b);

and g2(y,a,c);

and g3(z,b,c);

or g4(cout,x,y,z);

endmodule

endmodule

Still stressed from student homework?
Get quality assistance from academic writers!
Order now