Using your understanding of the principles of pipelining and its processing impact, solve the following problem:
For 5 stages of processors with given following latencies:
Fetch: 300 ps
Decode: 400 ps
Execute: 350 ps
Memory: 550 ps
Write back: 100 ps
Assuming that in pipelined design, each pipeline stage costs 20 ps extra for the registers between pipeline stages determine (a) cycle time, (b) latency and (c) throughput for non-pipelines and pipelined processor.
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