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Consider the sequential circuit whose state diagram is given Fig. 5.10, design this circuit using J-K flip flop according to the following procedure. a) Write the state table. b) Derive the flip-flop input and output equations. c) Draw the logic diagram. d) Draw the timing diagram for 5 clocks when x = 1 and the initial state is (00).
Expert Answer
a.
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b.
F1 and F2 are two flip flops and in is input or ‘x’
so the circut diagram truth table is
Out is output.
d.
| State | x | Next |
| 00 | 1 | 01 |
| 01 | 1 | 11 |
| 11 | 1 | 10 |
| 10 | 1 | 10 |
| 10 | 1 | 10 |
