Question & Answer: Given following cache: Show the end result after requesting following data: Read data from RAM address 00…..

Given following cache: Show the end result after requesting following data: Read data from RAM address 00010 Read data from RAM address 01000 Read data from RAM address 00110 Read data from RAM address 11010 Write data to RAM address 00010 Read data from RAM address 10110 Read data from RAM address 11010 Read data from RAM address 01000 Write data to RAM address 10110 If a read miss request ends up with a RAM load time of 100-ns and a hit with 4-ns, a write-hit with 3 ns and a write-miss with 10 ns, how long does the exercise take in sum? How many cycle would that be with a 4 GHz CPU?