Question & Answer: Dear expert hereI have already posted images of lecture in my previous question,now posting questions 2 again…..

. 30 points) Number conversion using a 2-level circuit. Design a 2-level AND-OR circuit that converts a 3-bit unsigned binary represented number v-u2u’u0 into a 4-bit two’s complement represented number T=tst2tite. The circuit is controlled by a control bit s to indicate the desired sign (positive or negative) of the output number T: .T is non-negative if and only ifs 1 * T is non-positive if and only if s = 0 For example: When U = 01 l and s = 1, T = 001 1 When U * 01 l and s = 0, T-1101 Your solution should include K-maps for t.t.t, and to. Boolean expressions derived from these K-maps in minimal SOP form, and a 2-level AND-OR circuit drawing. 2. 30 points) Show the 8-block cache structures for the primary memory access sequence: 4, 6, 5, 0, 6, 7, 8, 4, 2, 5, 7, 12, 5, 7. Calculate the total cycles, CPU execution time takes 1 cycle. Cachoe search time takes 1 cycle. Memory loading time takes 5 cycles. Mem.Blk.Hit/Miss Mapping Latency Total Mem.Blk. Hit/Miss Search Mem Load Execution Sum Total MemBlk HitiMiss Mapping Latency