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![Add PC[31-28] (Only for Branch) Add result Shift Uncondbranch left 2 Reg2Loc Branch MemRead Instruction [31-21] MemtoReg Control ALUO MemWrite ALUSrc RegWrite Instruction [9-5] Instruction [20-16 Read Read address register 1 PC ead u Read data 1 Zero Instruction xregister 2 [31-0] WriteRead register data 2 result ddress Read Instruction Instruction [4-0] LI memory Write data Registers Write memory Data Instruction [31-0) 32 Sign- 64 ALU control extend Instruction [31-21]](https://d2vlcm61l7u1fs.cloudfront.net/media%2F183%2F183d6272-8fa5-4168-9966-1e0924da1f95%2Fphp5w770Z.png)
Add PC[31-28] (Only for Branch) Add result Shift Uncondbranch left 2 Reg2Loc Branch MemRead Instruction [31-21] MemtoReg Control ALUO MemWrite ALUSrc RegWrite Instruction [9-5] Instruction [20-16 Read Read address register 1 PC ead u Read data 1 Zero Instruction xregister 2 [31-0] WriteRead register data 2 result ddress Read Instruction Instruction [4-0] LI memory Write data Registers Write memory Data Instruction [31-0) 32 Sign- 64 ALU control extend Instruction [31-21]please trace the datapath of each instruction on a new table for each to help me with clarity. (use data path above for each to trace over.)
a. ADDI X0, X1, #8
b. LSL X0, X1, #4
c. STUR X2, [X3, #8]
d. CBNZ X1, L1
e. B L2
Add PC[31-28] (Only for Branch) Add result Shift Uncondbranch left 2 Reg2Loc Branch MemRead Instruction [31-21] MemtoReg Control ALUO MemWrite ALUSrc RegWrite Instruction [9-5] Instruction [20-16 Read Read address register 1 PC ead u Read data 1 Zero Instruction xregister 2 [31-0] WriteRead register data 2 result ddress Read Instruction Instruction [4-0] LI memory Write data Registers Write memory Data Instruction [31-0) 32 Sign- 64 ALU control extend Instruction [31-21]
Expert Answer
a. The datapath for ADD instruction should look like
“ADDI X0, X1, #8”
Datapath :
if MEM[PC] == ADD Rd, Rn, Rm
GPR[Rd] <– GPR[Rn] + GPR[Rm]
PC <— PC + 4
The data path flow should look simmilar to
b. For the instruction LSL X0, X1, #4 datapath should be simmilar to LDUR instruction
c. For the instruction STUR X2, [X3, #8]
This is actually Store Instruction with syntax as
STUR Rtreg, [Rnreg, offset]
Here , Rterg is X2 , Rnreg is X3 and offset is #8 in HEx code .
The semantics should be ,
if MEM[PC]==STUR Rt, [Rn, offset]
EA = sign-extend(offset) + GPR[Rn]
MEM[EA] ← GPR[Rt]
PC ← PC + 4
And the datapath is like
and putting it all toggether the CBZ (Not taken ) i.e
the CBNZ X1, L1 instruction datapath should look like ,
And the last instruction is for running the loop .
