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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
VISVESWARAYA TECHNOLOGY UNIVERSITY, BELGAVI
JANASANGAM, BELGAVI-590018
An Internship Report On
SEEDED TRANCEIVER
Submitted by
MONISHA.M 1NH15EC053
Academic Year 2018-2019
Internship Carried Out
UNDER THE GUIDANCE OF
1.M.S.NEETHU JOHNY
ASSISTANT PROFESSOR
NEW HORIZON COLLEGE OF ENGINEERING
BANGALORE
2.MR.PRASANNA CHAUDHARY
COMPUTE SILICON
BENGALURU
DECLARATION
I Monisha.M (1NH15EC053) student of B.E in Electronics and communication and Engineering at New Horizon College of Engineering, Bangalore, hereby declare that this internship work entitled SERDES TRANSCEIVER is an original and bonafide work carried out by me at Compute Silicon, Bengaluru in particular internship during the academic year 2019-2020.
I also declare that, to the best of my knowledge the work reported here is not from any other thesis or dissertation on the basis of which the degree or award was conferred on an earlier occasion by any student.
Place: Bangalore
Date: 24/04/2019
MONISHA.M
(1NH15EC053)
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ACKNOWLEDGEMENT
The happiness and contempt that accompany the successful completion of any task would be incomplete without the mention of the people who made it possible and whose constant encouragement and guidance crowned our efforts with success.
I express my sincere gratitude to our respected internship guide Mr.Prasanna, Compute Silicon, Bengaluru for his valuable guidance and suggestions while carrying out the internship on SerdesTransceiver. I extend my gratitude to engineering staff and management in Compute Silicon, Bengaluru, Karnataka for their support.
Im proud to be the part of NHCE, the institution which stood with us in the successful completion of the internship. I take this opportunity to thank Department Of Electronics and Communication Engineering, NHCE for supporting me .I also thank my parents, group members, friends and almighty for constant support.
MONISHA.M
(1NH15EC053)
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CERTIFICATE OF INTERNSHIP FROM THE ORGANIZATION
INTRODUCTION
ABOUT COMPUTE SILICON
Compute Silicon is all started by Mr. Sanjeev Kumar Suman. Sanjeev has laboured in technology space for close to two a long time with pinnacle semiconductor agencies like Intel India, Texas units and couple of driving aspect new agencies (Deep learning and AI based totally generation)
They’re experts in fast and low power circuit systems. They take extends in reminiscence plan, sexually transmitted ailment mobile structure, simple shape and so forth. Their group has involvement in getting the best class PPA. They have got demonstrated statistics of excessive calibre and on time conveyances of their tasks.Their structure focuses are located in Bangalore and Noida. Their constructing organization is prepared for object improvement, execution effectiveness and on time conveyances.
Sanjeev Kumar Suman
Sanjeev has laboured in generation space for near two a long time with top semiconductor companies like Intel technology India , Texas and couple of using edge new agencies (Deep mastering and AI primarily based generation). Sanjeev is a former student of IIT Bombay and IIT Kanpur. He turned into All India Rank One holder in GATE exam.
Parimal Pawan Kumar
Parimal heads HR and Operations at Compute Silicon. He has over 15 years of company involvement inside the fields of Human aid and administration. He has laboured extensively in IT, Telecom, booklet and schooling enterprise for exceptional global companies. He holds a double PG degree within the board with the specialization in human asset.
AREA OF EXPERTISE IN COMPUTE SILICON
SRAM Compiler Memory
Excellent Architectures
overall performance Optimized
ultra-low power circuit
Standard(std.) cell
great process bolsters
Optimized and mechanized streams
best quality on time conveyances
Format design
SRAM, ROM, register files
Standard cell
excessive speed Serdes
Custom Cache memory
location and performance advanced
Optimized circuit patterns
appropriate and mapped constructing alternate offs
Custom register files and ROM layout
high-quality in class
overall superior performance
extremely-low electricity consumption strategies
simple and mixed flag design
offerings for a huge range of easy IP
power the board squares
statistics converters, LDO’s and so on.
DESCRIPTION OF INTERNSHIP CARRIED OUT
Compute Silicon is a expert in fast and low power circuit systems. They take extends in reminiscence plan, sexually transmitted ailment mobile structure, simple shape and so forth. Their group has involvement in getting the best class PPA. They have got demonstrated statistics of excessive calibre and on time conveyances of their tasks.Their structure focuses are located in Bangalore and Noida. Their constructing organization is prepared for object improvement, execution effectiveness and on time conveyance .
First day I was given a brief description on basic concepts of VLSI and its design flow.
Later we got a brief insight on state machine diagram,FSM and coding of FSM using Verilog.
The main aim of the internship was to work on one of the blocks of System On Chip (S0C).
Some of the blocks of SOC are memory controllers, SERDES transmitter, SPI, SERDES receiver and MAC.
I was given the topic of SERDES-receiver and was asked to work on it.
In this internship I learnt about the various blocks of Serdes and the functionality of this block
Codes for few of the blocks were written in Verilog and executed in the Xilinx software.
GENERAL ROLES AND RESPONSIBILITIES OF INTERN
Show the best level of professionalism, which includes arriving on time for particular meetings, notifying the guide of any deviations from the mounted schedule, and dressing to the requirements of the organization and the work being completed. Respect the agencys reporting policy and observe the guidelines and processes of the organization.
Communicate properly with the guide accept and apply corrections and suggestions to daily work to become a good intern.
Communicate with the guide any issues that may affect your performance of assigned task and work.
Appreciate diversity in all of its forms and respect various social and political viewpoints; do not discriminate on the basis of race, creed, color, sex, religion, age, nation/ethnic origin, disability, or sexual orientation.
Uphold the High Point University Conduct Code and act in an ethical manner when on and off-campus and while representing the host organization.
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TECHNICAL TAKE-AWAYS OF THE INTERNSHIP
SERDES RECEIVER
The serializer circuit gets the 8-bit data in parallel mode and delivers the 10-bit coded serialized information to deserializer .Deserializer decodes the facts and gives you the eight-bit parallel information.
APPLICATIONS OF SERDES:
I. It is used for communication in VLSI chips
II. DVI/HDMI
III. Serial ATA
IV. USB 3.0
V. Gigabit Ethernet
VI. PCI Express
BLOCK DIAGRAM OF SERDES:
Serializer includes three purposeful blocks specifically
Eight-bit D-Flip Flop:
This block is used to take eight-bits as enter the use of 8 D-flip Flops linked in parallel.
8b to 10b encoder:
This block encodes 8bits of facts to 10 bits. that is achieved to make sure a couple of facet transitions and DC stability (balanced wide variety of transmitted ones and zeros).
10bit parallel to serial converter:
10 bit is converted into serial shape with the assist of parallel to serial converter. This good judgment uses a clock which helps serially clock the packets out.
Deserializer includes following purposeful blocks:
10bit serial to parallel converter:
The Deserializer makes use of the reference clock to screen the recovered clock from the bit stream. A serial to parallel converter allows to convert the serial sign into 10 bit parallel signal.
10b to 8b decoder:
It decodes 10bit information to 8bit.
Eight-bit D-Flip Flop:
It offers the eight-bit output with the help of eight turn flops related in parallel.
8-BIT D-FLIP FLOP
In Serdes 8-bit D-flip flop is used to transmit and get hold of 8bit records in parallel at serializer and deserializer respectively.
8B-10B ENCODER
The 8b/10b coding scheme became by using Albert X. Widmer and Peter A. Franaszek of IBM organization in 1983.
This coding scheme is used for excessive-velocity serial records transmission. The encoder at the transmitter side maps the 8-bit parallel statistics input to ten-bit output.
DC Balance
A DC-balanced serial records movement method that wide variety of zeros and 1s for a given period of statistics stream is equal. DC-stability is important for certain media because it prevents a fee that could increase within the media.
8b/10b Code Mapping
The 8b/10b encoder converts 8-bit code corporations into 10-bit codes. The code groups include 256 records characters named Dx.y and 12 manipulate characters named Kx.y.
The coding scheme breaks the authentic eight-bit records into blocks, 3 most substantial bits (y) and five least widespread bits (x).
From the most massive bit to the least considerable bit, they may be named as H, G, F and E, D, C, B, A.
The three-bit block is encoded into 4 bits named j, h, g, and f.
The five-nit block is encoded into 6 bits named i, e, d, c, b, a.
The table shows 8b-10b encoded data:
The transmitter assumes a poor running (RD-) at start up.
while an eight-bit data is encoding, the encoder will use the RD- column for encoding.
If the 10-bit records been encoded is disparity neutral, the jogging Disparity will no longer be changed and the RD- column will nevertheless be used.
In any other case, the running Disparity might be modified and the RD+ column will be used as a substitute.
Simillarly, if the contemporary walking Disparity is fantastic (RD+) and a disparity impartial 10-bit records is encoded, the walking Disparity will nonetheless be RD+.
Otherwise , it’ll be changed from RD+ again to RD- and the RD- column may be used once more.
SIMULATION RESULTS OF 8B-10B ENCODER:
10B/8B DECODER
Many serial information transmission make use of 8b/10b encoding to make sure suf?cient information transitions for clock recuperation.
This coding scheme is used for high-pace serial statistics transmission.
The decoding procedure is relative direct and less difficult compared to the encoding technique.
Inside the interpreting process the decoder might be designed with the entire viable encoded output sample.
In the decoding manner, the disparity checking may be applied for blunders checker to make certain the encoded facts is DC balance.
PIN DESCRIPTION TABLE
10b/8b decoder simulation results
10 BIT PARALLEL TO SERIAL CONVERTER
This block encodes 8bits of information to 10 bits. that is carried out to ensure a couple of side transitions and DC balance (balanced number of transmitted ones and zeros).
RTL CODE:
module piso1(clk1,rst1,in,out1);
input clk1,rst1;
input[9:0]in1;
output 1out1;
reg 1out1;
reg1[9:0] temp1;
[email protected](posedge clk1,posedge rst1)
begin
if(rst1==1b1)
begin
q1
