 Assume the following information about a 2-level memory hierarchy system.

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Memory capacity is 4 GB (G=2^30).

Cache capacity is 64 KB (K=2^10).

Block offset size is 8 bits.

Assuming that the CPU has generated the physical address X = (2293936063)10, answer the following questions.

a. If direct mapped is used, where will the block containing address X reside in cache? In other words, what is the cache address for the block containing address X?

b. If 2-way set associative is used, how many blocks are in the cache?

c. What is the memory physical address size? In other words, how many bits are in each physical address?

d. If direct mapped is used, how many segments are in the memory?

e. If direct mapped is used, what is the size of each segment in bytes?

f. If 2-way set associative is used, what is the size of each segment in bytes?

g. What is the block offset value (not size) for this physical address (i.e. X)? h. If direct mapped is used, what is the index size (not value)?

i. If 2-way set associative is used, what is the index size (not value)?

So X = (2293936063)10

or X = (1000 1000 1011 1010 1010 1111 1011 1111)2

a) For Direct mapped cache:
Block size = 8B
Cache size = 64KB
therefore
numbers of block: 8192

offset: 3bit (log(8))
index: 13bit (log(8192))

Therefore index field of X is 1010111110111

b) Number of blocks does not change with the number of sets in a n-way-set-associative cache. so we still have 8192 blocks in the cache. But we have 4096 sets

c) Since the memory capacity is 4GB, we need 32bits (log2(4*230)) for addressing the whole memory space. So the address width is 32bits

d) We have 8192 segments in case of directmaped. Every addresses in the memory will be mapped to one of the 8192 cache line.

e) Size of each segment is 216 bytes

f) In case of 2-way set associative, we have half of 8192 segments, or 4096 segments. And segment size doubles to 217 bytes

g) offset is (111)2 or 8

h) index is: (1010111110111)2 or 5623

i)index is: (010111110111)2 or 1527