 Assume the following information about a 2-level memory hierarchy system.

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Memory capacity is 4 GB (G=2^30).

Cache capacity is 64 KB (K=2^10).

Block offset size is 8 bits.

Assuming that the CPU has generated the physical address X = (2293936063)10, answer the following questions.

a. If direct mapped is used, where will the block containing address X reside in cache? In other words, what is the cache address for the block containing address X?

b. If 2-way set associative is used, how many blocks are in the cache?

c. What is the memory physical address size? In other words, how many bits are in each physical address?

d. If direct mapped is used, how many segments are in the memory?

e. If direct mapped is used, what is the size of each segment in bytes?

f. If 2-way set associative is used, what is the size of each segment in bytes?

g. What is the block offset value (not size) for this physical address (i.e. X)? h. If direct mapped is used, what is the index size (not value)?

i. If 2-way set associative is used, what is the index size (not value)?

Solution:

Information:

• Memory capacity is 4GB i.e 230 * 22 = 232 B.
• Cache capacity = 64KB i.e 210 * 26 = 216 B.
• Block offset size is 8 bit.
• In direct map chacke memory, the cache is divided into three parts: Tag, Index to identify each cache line, and block offset.
• As offset denotes block size in the cache, block size in cache = 28 B.
• Cache line = cache size / Block size = 64KB / 28 B = 216 / 28 = 28 .
• Therefore Number of index bit = log 2 28 = 8 bit.
• Number of tag bits in cache = number of main memory address bit – (index + offset) = 32 – (8 +8) = 16 bit.

Solution:

Question a:

The physical address X = (2293936063)10 = (10001000101110101010111110111111)2

The above address is divided as follows:

 Tag(16 bits) Index(8 bits) Block offset(8 bits) 1000 1000 1011 1010 1010 1111 1011 1111

Therefore the cache address for the cache line where the block containing address X is stored is (1010 1111)2 = (175)10

Question b:

In a two-way set associative mapping, each index indicates two data words and tags associated to them.

Therefore in each cache line it stores two data words and tags associated to them.

Therefore number of cache lines or blocks = number of cache line in direct map / 2 = 28 / 2 = 27.

Question c:

Main memory capacity is 4 GB = 230 * 4 = 232 B.

Therefore number of bits in main memory address is 32-bit.

Question d:

As each word size is 32 bit, therefore number of segments in main memory is:

main memory size / word size = 232 / 25 = 227.

Therefore main memory contains 227 segments.

Question e:

if direct mapped is used each segment contains 32 bit word.

Therefore size of each segment would be 32 bit or 4 byte.

Question f:

In a 2-way associative mapping, the cache is mapped with 2 data words and tags associated to them. The main memory mapping is kept unchanged.

Therefore segment size would be 4byte.

Question g:

As I mentioned before, for address X, the address is divided as:

 Tag(16 bits) Index(8 bits) Block offset(8 bits) 1000 1000 1011 1010 1010 1111 1011 1111

Therefore the block offset value for the physical address X is (1011 1111)2 = (191)10 .

Question h:

As mentioned earlier, if direct mapped is used the size of the index will be 8-bit.

Question i:

The index size will not be changed for 2-way associative mapping. Therefore index size will be 8-bit.